# $Revision: 1.1.8.1 $ Model { Name "FS_4_FDI" Version 7.7 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.149" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" PreLoadFcn "initpend" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" MaxMDLFileLineLength 120 Created "Tue Sep 14 01:24:40 2004" Creator "The MathWorks Inc." UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "simani" ModifiedDateFormat "%" LastModifiedDate "Tue Nov 29 15:54:56 2016" RTWModifiedTimeStamp 402335627 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines on ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.11.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.11.0" StartTime "0" StopTime "1500" AbsTol "1e-6" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "0.02" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" ConcurrentTasks off Solver "ode45" SolverName "ode45" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.11.0" Decimation "1" ExternalInput "[]" FinalStateName "xFinal" InitialState "[]" LimitDataPoints off MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput off SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime off ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.11.0" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction off BooleanDataType off ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off UseSpecifiedMinMax off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 5 Version "1.11.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "none" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "none" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskCondExecSysMsg "none" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "None" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.11.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown on ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.11.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 8 Version "1.11.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.11.0" Array { Type "Cell" Dimension 8 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateSLWebview" Cell "GenerateCodeMetricsReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime on GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.11.0" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.11.0" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" FunctionExecutionProfile off CodeExecutionProfiling off ERTCodeCoverageTool "None" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" ExtraOptions "-aEnforceIntegerDowncast=1 -aPrefixModelToSubsysFcnNames=1 " CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 200, 85, 1080, 715 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType Fcn Expr "sin(u[1])" SampleTime "-1" } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ParamMin "[]" ParamMax "[]" ParamDataTypeStr "Inherit: Same as input" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Ground } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Integrator ExternalReset "none" InitialConditionSource "internal" InitialCondition "0" LimitOutput off UpperSaturationLimit "inf" LowerSaturationLimit "-inf" ShowSaturationPort off ShowStatePort off AbsoluteTolerance "auto" IgnoreLimit off ZeroCross on ContinuousStateAttributes "''" } Block { BlockType Mux Inputs "4" DisplayOption "none" UseBusObject off BusObject "BusObject" NonVirtualBus off } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" Variant off GeneratePreprocessorConditionals off } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } Block { BlockType UniformRandomNumber Minimum "-1" Maximum "1" Seed "0" SampleTime "-1" VectorParams1D on } Block { BlockType UnitDelay X0 "0" InputProcessing "Inherited" SampleTime "1" StateMustResolveToSignalObject off RTWStateStorageClass "Auto" } } System { Name "FS_4_FDI" Location [2, 99, 1260, 767] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "219" Block { BlockType SubSystem Name "Dynamic process" SID "82" Ports [2, 1] Position [395, 57, 580, 193] BackgroundColor "lightBlue" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Dynamic process" Location [47, 153, 1035, 656] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "u1" SID "83" Position [15, 18, 45, 32] BackgroundColor "red" IconDisplay "Port number" } Block { BlockType Inport Name "u2" SID "84" Position [175, 248, 205, 262] BackgroundColor "red" Port "2" IconDisplay "Port number" } Block { BlockType Sum Name "Add" SID "85" Ports [2, 1] Position [515, 185, 535, 205] IconShape "round" Inputs "|++" SaturateOnIntegerOverflow off } Block { BlockType Constant Name "Constant0" SID "86" Position [60, 95, 90, 125] BlockMirror on ShowName off Value "0" } Block { BlockType Fcn Name "Fcn1" SID "87" Position [465, 65, 505, 85] ShowName off Expr "(u[1]/m - g*sin(u[3])*cos(u[3]) + l*power(u[2],2)*sin(u[3]))/(M/m + power(sin(u[3]),2))" } Block { BlockType Fcn Name "Fcn2" SID "88" Position [460, 185, 500, 205] ShowName off Expr "(-u[1]*cos(u[3])/m + (M+m)*g*sin(u[3])/m - l*power(u[2],2)*sin(u[3])*cos(u[3]))/(l*(M/m + power(sin(u[3])" ",2)))" } Block { BlockType Gain Name "Feedback" SID "89" Position [190, 49, 240, 81] Gain "K" Multiplication "Matrix(K*u)" SaturateOnIntegerOverflow off } Block { BlockType Integrator Name "Integrator1" SID "90" Ports [1, 1] Position [640, 65, 660, 85] ShowName off InitialCondition "x0" } Block { BlockType Integrator Name "Integrator2" SID "91" Ports [1, 1] Position [640, 185, 660, 205] ShowName off InitialCondition "theta0" } Block { BlockType Integrator Name "Integrator3" SID "92" Ports [1, 1] Position [555, 185, 575, 205] ShowName off } Block { BlockType Integrator Name "Integrator4" SID "93" Ports [1, 1] Position [560, 65, 580, 85] ShowName off } Block { BlockType Mux Name "Mux" SID "94" Ports [3, 1] Position [390, 179, 420, 211] ShowName off Inputs "3" } Block { BlockType Mux Name "Mux1" SID "95" Ports [3, 1] Position [395, 59, 425, 91] ShowName off Inputs "3" } Block { BlockType Mux Name "Mux2" SID "96" Ports [4, 1] Position [405, 310, 410, 405] BlockMirror on ShowName off DisplayOption "bar" } Block { BlockType Mux Name "Mux3" SID "97" Ports [4, 1] Position [100, 12, 105, 83] ShowName off DisplayOption "bar" } Block { BlockType Sum Name "Sum2" SID "98" Ports [2, 1] Position [140, 34, 160, 96] ShowName off Inputs "+-" } Block { BlockType Terminator Name "Terminator" SID "99" Position [810, 115, 830, 135] } Block { BlockType Terminator Name "Terminator1" SID "100" Position [720, 185, 740, 205] } Block { BlockType Terminator Name "Terminator2" SID "101" Position [635, 265, 655, 285] } Block { BlockType Outport Name "y" SID "102" Position [915, 68, 945, 82] BackgroundColor "red" IconDisplay "Port number" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Fcn2" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Fcn1" DstPort 1 } Line { SrcBlock "Fcn1" SrcPort 1 DstBlock "Integrator4" DstPort 1 } Line { SrcBlock "Integrator4" SrcPort 1 Points [20, 0] Branch { DstBlock "Integrator1" DstPort 1 } Branch { Points [0, 50; 180, 0] Branch { Points [0, 220] DstBlock "Mux2" DstPort 2 } Branch { DstBlock "Terminator" DstPort 1 } } } Line { SrcBlock "Feedback" SrcPort 1 Points [30, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 120] DstBlock "Mux" DstPort 1 } } Line { SrcBlock "Integrator3" SrcPort 1 Points [20, 0] Branch { Points [0, -35; -295, 0] Branch { Points [0, -85] DstBlock "Mux1" DstPort 2 } Branch { Points [0, 35] DstBlock "Mux" DstPort 2 } } Branch { DstBlock "Integrator2" DstPort 1 } Branch { Points [0, 80] Branch { Points [0, 120] DstBlock "Mux2" DstPort 4 } Branch { DstBlock "Terminator2" DstPort 1 } } } Line { SrcBlock "Integrator2" SrcPort 1 Points [15, 0] Branch { Points [0, -50; -335, 0] Branch { Points [0, -60] DstBlock "Mux1" DstPort 3 } Branch { Points [0, 60] DstBlock "Mux" DstPort 3 } } Branch { Points [0, 175] DstBlock "Mux2" DstPort 3 } Branch { DstBlock "Terminator1" DstPort 1 } } Line { SrcBlock "Add" SrcPort 1 DstBlock "Integrator3" DstPort 1 } Line { SrcBlock "Fcn2" SrcPort 1 DstBlock "Add" DstPort 1 } Line { SrcBlock "Integrator1" SrcPort 1 Points [195, 0] Branch { DstBlock "y" DstPort 1 } Branch { Points [0, 245] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "u2" SrcPort 1 Points [315, 0] DstBlock "Add" DstPort 2 } Line { SrcBlock "Sum2" SrcPort 1 DstBlock "Feedback" DstPort 1 } Line { SrcBlock "Constant0" SrcPort 1 Points [-5, 0; 0, -40] Branch { Points [0, -30] Branch { Points [0, 15] DstBlock "Mux3" DstPort 3 } Branch { DstBlock "Mux3" DstPort 2 } } Branch { DstBlock "Mux3" DstPort 4 } } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Sum2" DstPort 1 } Line { SrcBlock "u1" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 Points [-285, 0; 0, -275] DstBlock "Sum2" DstPort 2 } Annotation { Name "Internal feedback" Position [267, 324] } } } Block { BlockType Reference Name "Fuzzy Logic \nController" SID "219" Ports [1, 1] Position [565, 451, 625, 499] BackgroundColor "green" LibraryVersion "1.179" FontName "Arial" SourceBlock "fuzblock/Fuzzy Logic \nController" SourceType "FIS" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off fis "FM05" } Block { BlockType Ground Name "Ground" SID "109" Position [275, 150, 295, 170] } Block { BlockType Ground Name "Ground1" SID "214" Position [30, 205, 50, 225] } Block { BlockType Ground Name "Ground2" SID "215" Position [605, 230, 625, 250] } Block { BlockType Reference Name "Input fault" SID "213" Ports [2, 1] Position [90, 115, 115, 250] LibraryVersion "1.236" SourceBlock "simulink/Signal\nRouting/Manual Switch" SourceType "Manual Switch" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off sw "0" action "0" varsize off } Block { BlockType Mux Name "Mux1" SID "110" Ports [5, 1] Position [510, 331, 515, 619] ShowName off Inputs "5" DisplayOption "bar" } Block { BlockType Mux Name "Mux2" SID "209" Ports [2, 1] Position [1070, 516, 1075, 554] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Mux Name "Mux3" SID "60" Ports [2, 1] Position [950, 206, 955, 244] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Reference Name "Output fault" SID "216" Ports [2, 1] Position [665, 140, 690, 275] LibraryVersion "1.236" SourceBlock "simulink/Signal\nRouting/Manual Switch" SourceType "Manual Switch" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off sw "0" action "0" varsize off } Block { BlockType UniformRandomNumber Name "Random \nReference" SID "107" Position [110, 74, 140, 106] BackgroundColor "green" Minimum "-0.3" Maximum "0.3" Seed "1" SampleTime "10" } Block { BlockType Scope Name "Scope1" SID "210" Ports [1] Position [1115, 519, 1145, 551] ShowName off Floating off Location [188, 136, 1214, 722] Open off NumInputPorts "1" List { ListType AxesTitles axes1 "%" } DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "Scope4" SID "59" Ports [1] Position [995, 209, 1025, 241] ShowName off Floating off Location [188, 136, 1214, 722] Open off NumInputPorts "1" List { ListType AxesTitles axes1 "%" } SaveName "ScopeData4" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "Scope5" SID "61" Ports [1] Position [845, 54, 875, 86] ShowName off Floating off Location [188, 105, 1214, 724] Open off NumInputPorts "1" List { ListType AxesTitles axes1 "%" } SaveName "ScopeData5" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "Scope8" SID "70" Ports [1] Position [1135, 289, 1165, 321] ShowName off Floating off Location [188, 105, 1214, 724] Open off NumInputPorts "1" List { ListType AxesTitles axes1 "%" } SaveName "ScopeData8" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Step Name "Step\nFault" SID "212" Position [25, 135, 55, 165] BackgroundColor "red" Time "750" SampleTime "0" } Block { BlockType Step Name "Step\nFault1" SID "217" Position [600, 160, 630, 190] BackgroundColor "red" Time "750" After "-1" SampleTime "0" } Block { BlockType Sum Name "Sum1" SID "69" Ports [2, 1] Position [995, 295, 1015, 315] ShowName off IconShape "round" Inputs "|+-" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum2" SID "211" Ports [2, 1] Position [165, 170, 185, 190] BlockRotation 270 BlockMirror on BackgroundColor "red" NamePlacement "alternate" ShowName off IconShape "round" Inputs "++|" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum3" SID "218" Ports [2, 1] Position [725, 200, 745, 220] BlockRotation 270 BlockMirror on BackgroundColor "red" NamePlacement "alternate" ShowName off IconShape "round" Inputs "++|" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType UnitDelay Name "Unit Delay" SID "113" Position [275, 513, 310, 547] InputProcessing "Elements as channels (sample based)" SampleTime "Ts" } Block { BlockType UnitDelay Name "Unit Delay1" SID "116" Position [275, 403, 310, 437] InputProcessing "Elements as channels (sample based)" SampleTime "Ts" } Block { BlockType UnitDelay Name "Unit Delay2" SID "118" Position [395, 568, 430, 602] InputProcessing "Elements as channels (sample based)" SampleTime "Ts" } Block { BlockType UnitDelay Name "Unit Delay3" SID "121" Position [395, 458, 430, 492] InputProcessing "Elements as channels (sample based)" SampleTime "Ts" } Line { SrcBlock "Random \nReference" SrcPort 1 Points [30, 0] Branch { Points [0, -60; 625, 0; 0, 40] Branch { DstBlock "Scope5" DstPort 1 } Branch { Points [0, 145] DstBlock "Mux3" DstPort 1 } } Branch { DstBlock "Dynamic process" DstPort 1 } Branch { DstBlock "Sum2" DstPort 2 } } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Scope4" DstPort 1 } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Scope8" DstPort 1 } Line { SrcBlock "Ground" SrcPort 1 DstBlock "Dynamic process" DstPort 2 } Line { SrcBlock "Unit Delay" SrcPort 1 Points [40, 0] Branch { Points [0, 55] DstBlock "Unit Delay2" DstPort 1 } Branch { DstBlock "Mux1" DstPort 4 } } Line { SrcBlock "Unit Delay1" SrcPort 1 Points [45, 0] Branch { Points [0, 55] DstBlock "Unit Delay3" DstPort 1 } Branch { DstBlock "Mux1" DstPort 2 } } Line { SrcBlock "Unit Delay2" SrcPort 1 DstBlock "Mux1" DstPort 5 } Line { SrcBlock "Unit Delay3" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Fuzzy Logic \nController" SrcPort 1 Points [375, 0] Branch { DstBlock "Sum1" DstPort 2 } Branch { Points [0, 70] DstBlock "Mux2" DstPort 2 } } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Scope1" DstPort 1 } Line { SrcBlock "Sum2" SrcPort 1 Points [0, 170] Branch { Points [0, 55] DstBlock "Unit Delay1" DstPort 1 } Branch { DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "Input fault" SrcPort 1 DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Step\nFault" SrcPort 1 DstBlock "Input fault" DstPort 1 } Line { SrcBlock "Ground1" SrcPort 1 DstBlock "Input fault" DstPort 2 } Line { SrcBlock "Output fault" SrcPort 1 DstBlock "Sum3" DstPort 1 } Line { SrcBlock "Step\nFault1" SrcPort 1 DstBlock "Output fault" DstPort 1 } Line { SrcBlock "Ground2" SrcPort 1 DstBlock "Output fault" DstPort 2 } Line { SrcBlock "Dynamic process" SrcPort 1 Points [150, 0] DstBlock "Sum3" DstPort 2 } Line { SrcBlock "Sum3" SrcPort 1 Points [0, 10] Branch { Points [0, 70] Branch { Points [-640, 0; 0, 225] DstBlock "Unit Delay" DstPort 1 } Branch { Points [0, 220] DstBlock "Mux2" DstPort 1 } Branch { DstBlock "Sum1" DstPort 1 } } Branch { DstBlock "Mux3" DstPort 2 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Fuzzy Logic \nController" DstPort 1 } Annotation { Name "Residual" Position [1073, 291] } } }